1. Technical Field
This invention relates generally to digital circuitry and more particularly to a system and associated method of operation in a programmable gate array for detecting error conditions in the programmable gate array, the system and associated method providing high speed error detection with minimized overhead.
2. Related Art
The use of state logic within digital systems is well known. Many modern integrated circuits use some form of state logic to execute their specific functions. Circuitry using state logic includes, for example, microprocessors, digital signal processors, application specific integrated circuits, micro-controller units and various other digital circuits. State logic typically includes state machines and combining logic. State machines may include registers, latches and other circuits employed to represent one or more state bits. The combining logic interconnects the state machines and intercouples inputs to execute desired state machine logic. External inputs are provided to the combining logic per a state machine logic design while outputs are derived from the state bits and output per the state machine logic design.
In many applications, for example in the communications industry, programmable gate arrays are used within communication system elements to execute particular state machine logic. In many applications, the programmable gate arrays are field programmable so that they may be easily reprogrammed as required. Field programmable gate arrays ("FPGAs") are used in, for example, switching systems, switching equipment, mobile terminals, radio control circuitry, and various other elements that may reside within such communication systems.
FIG. 1 generically illustrates a FPGA 100 that may be employed within various communication system elements. The FPGA 100 includes a plurality of logic blocks 102 connected via routing resources 104A and 104B to, in combination, execute programmed logic, which may include state machine logic. Each of the logic blocks 102 receives inputs 106A and 106B and produces outputs 112A and 112B. The inputs 106A and 106B may be either inputs received externally from the FPGA 100 or outputs of other logic blocks 102. Further, outputs 112A and 112B may be outputs provided external to the FPGA 100 or provided as inputs to other logic blocks 102.
Each of the logic blocks 102 may include, for example, lookup tables (LUTs) 108A and 108B and registers 110A and 110B. Each of the registers 110A and 110B produces one or more state bits. In combination, these state bits represent a state of the logic block 102 while, in combination, the states of the logic blocks 102 produce a system state. The LUTs 108A and 108B receive the inputs 106A and 106B, respectively, and execute logic functions to produce either inputs to the registers 110A and 110B or the outputs 112A and 112B, based upon the programming of the multiplexing elements 107A and 107B. Programmed in a bypass mode, the multiplexing elements 107A and 107B bypass outputs from the LUTs 108A and 108B to the outputs 112A and 112B. In such a bypass mode, the logic block 102 executes only combinational logic without producing state bits. In a non-bypass mode, outputs from the LUTs 108A and 108B route via the multiplexing elements 107A and 107B to the registers 110A and 110B to produce the state bits. The LUTs 108A and 108B, the multiplexing elements 107A and 107B and the routing resources 104A and 104B are programmed at startup or reset so that the FPGA 100 performs a desired logic operation which may include state machine logic operation. Due to its reprogrammable construction, the FPGA 100 may be reprogrammed as required without removing the FPGA 100 from its host system.
During normal operations, the FPGA 100 executes it programmed state machine logic without error. However, in the presence of noise and other system anomalies, operation of the FPGA 100 may become disrupted. During such disruption, the FPGA 100 may enter an erroneous system state. Such erroneous system state causes the outputs 112A and 112B produced by the FPGA to also be erroneous, potentially disrupting operation of the host system. Thus it is desirable to determine when an erroneous state or states are entered by the FPGA so that the FPGA may be reset to a known valid state and to commence operation therefrom.
Some prior art FPGAs incorporated error detection methodologies that were incorporated into the state machine logic. However, these FPGAs used a binary encoded method for implementing the state machine logic, such programming being inherently slow. Thus, with the error detection functions, the FPGAs failed to provide satisfactory performance.
Thus, in speed sensitive applications, FPGAs may be programmed to implement state machine logic using one-hot encoding. In one-hot encoding, the plurality of logic blocks 102 operate in cooperation such that only a single one of the state bits of the system state is logic high at any time. Further, in one-hot encoded operation, the overall speed of operation of the FPGA increases significantly as compared to the speed of binary encoded state machine logic implemented in FPGAs. However, in one-encoding, the number of erroneous states, as compared to the number of erroneous states in a binary encoded state machine, increases significantly. For example, in a ten state programmable gate array, there are 1,014 undefined states. To detect such large number of undefined states using conventional techniques wherein error logic is programmed along with operating logic would decrease the speed of operation to such an extent so as to defeat the purpose of one-hot encoding.
Thus, there is a need in the art for a system and associated methodology that expeditiously determines whether a one-hot programmed gate array and other gate arrays is properly operating and to initiate a reset upon detection of an erroneous operating condition.